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Message-ID: <4CBBB3EC.9000609@linux.intel.com>
Date: Mon, 18 Oct 2010 10:41:48 +0800
From: Chen Gong <gong.chen@...ux.intel.com>
To: "Koornstra, Reinoud" <koornstra@...com>
CC: "Rafael J. Wysocki" <rjw@...k.pl>, Greg KH <gregkh@...e.de>,
Sameer Nanda <snanda@...omium.org>,
"lenb@...nel.org" <lenb@...nel.org>,
"stefan.bader@...onical.com" <stefan.bader@...onical.com>,
"brad.figg@...onical.com" <brad.figg@...onical.com>,
"apw@...onical.com" <apw@...onical.com>,
"linux-acpi@...r.kernel.org" <linux-acpi@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] ACPI: Read TSC upon resume
δΊ 10/16/2010 11:03 AM, Koornstra, Reinoud ει:
>> -----Original Message-----
>> From: linux-acpi-owner@...r.kernel.org [mailto:linux-acpi-
>> owner@...r.kernel.org] On Behalf Of Rafael J. Wysocki
>> Sent: Thursday, October 07, 2010 2:44 PM
>> To: Greg KH
>> Cc: Sameer Nanda; lenb@...nel.org; stefan.bader@...onical.com;
>> brad.figg@...onical.com; apw@...onical.com; linux-acpi@...r.kernel.org;
>> linux-kernel@...r.kernel.org
>> Subject: Re: [PATCH] ACPI: Read TSC upon resume
>>
>> On Thursday, October 07, 2010, Greg KH wrote:
>>> On Thu, Oct 07, 2010 at 11:05:21AM -0700, Sameer Nanda wrote:
>>>> On Thu, Oct 7, 2010 at 10:46 AM, Greg KH<gregkh@...e.de> wrote:
>>>>> On Thu, Oct 07, 2010 at 10:43:34AM -0700, Sameer Nanda wrote:
>>>>>> On Wed, Oct 6, 2010 at 7:19 PM, Greg KH<gregkh@...e.de> wrote:
>>>>>>> And are you always going to be printing this out? Why do we
>> want to
>>>>>>> know this every time?
>>>>>>>
>>>>>>
>>>>>> Yes, every time. This helps track variance in BIOS resume times
>> within a
>>>>>> single boot.
>>>>>
>>>>> Is that really something that users can do something about?
>>>>
>>>> Aside from complaining to the BIOS vendors, no :)
>>>
>>> Then I would not recommend adding this patch, as it is irrelevant for
>>> 99.9999% of all Linux users.
>>
>> It may be somewhat useful, but the rdtscll() call seems to be x86-
>> specific, in
>> which case it shouldn't be used at this place.
>
> Also, in the case of an intel core 2 duo cpu, the tsc is not stable, hence upon resume the cpu is spinning up and the first tsc's will be slower.
> During idle-time the tsc will not be incremented. The tsc is only stably incremented upon 100% cpu usage. It also doesn't increment faster in turbo mode in case of some core 2 duo and certainly the Nehalem cpu's. Calculating in time in terms of tsc might not be so reliable.
>
If I'm wrong, please feel free to fix me.
I have 2 questions to your answer:
1. CPU has a flag named constant_tsc to keep TSC always working in a
constant way, so it is irrelvant to the CPU freq. whether in turbo mode
or any P-state CPU currently belongs to, TSC should be not affected.
IIRC, this flag should exist long before, at least before Core 2 duo. If
so, TSC shoule be stable in this kind of environment.
2. though during idle-time TSC will not be incremented, here I want to
remind it is right before Westmere (TSC not always running), and you
mentioned "upon resume the cpu is spinning up and the first tsc's will
be slower", I don't know if this commit cd7240c0b can fix it up.
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