linux-kernel - Re: [PATCH resend 5/9] MIPS: sync after cacheflush

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Message-ID: <AANLkTimmatKpOFATCPDxthN-9pZzzXRAOnLGR1_348=r@mail.gmail.com>
Date:	Mon, 18 Oct 2010 12:41:20 -0700
From:	Kevin Cernekee <cernekee@...il.com>
To:	Ralf Baechle <ralf@...ux-mips.org>
Cc:	Shinya Kuribayashi <skuribay@...ox.com>, linux-mips@...ux-mips.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH resend 5/9] MIPS: sync after cacheflush

On Mon, Oct 18, 2010 at 12:19 PM, Ralf Baechle <ralf@...ux-mips.org> wrote:
> I'm trying to get a statement from the MIPS architecture guys if the
> necessity to do anything beyond a cache flush is an architecture violation.

IMO such a requirement would be unnecessarily strict.  Larger flushes
(e.g. page at a time) tend to benefit from some form of pipelining or
write gathering.  Forcing the processor to flush exactly 32 bytes at a
time, synchronously, could really slow things down and thrash the
memory controller.

I have not been able to find any official statement from MIPS that
says that CACHE + SYNC should be used, but that seems like the most
intuitive way to implement things on the hardware side.
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