linux-kernel - Re: [PATCH] tracing: Cleanup the convoluted softirq tracepoints

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Date:	Tue, 19 Oct 2010 15:49:14 -0700
From:	"H. Peter Anvin" <hpa@...or.com>
To:	Mathieu Desnoyers <mathieu.desnoyers@...icios.com>
CC:	Steven Rostedt <rostedt@...dmis.org>,
	Thomas Gleixner <tglx@...utronix.de>,
	Koki Sanagi <sanagi.koki@...fujitsu.com>,
	Peter Zijlstra <peterz@...radead.org>,
	Ingo Molnar <mingo@...e.hu>,
	Frederic Weisbecker <fweisbec@...il.com>,
	nhorman@...driver.com, scott.a.mcmillan@...el.com,
	laijs@...fujitsu.com, LKML <linux-kernel@...r.kernel.org>,
	eric.dumazet@...il.com, kaneshige.kenji@...fujitsu.com,
	David Miller <davem@...emloft.net>, izumi.taku@...fujitsu.com,
	kosaki.motohiro@...fujitsu.com,
	Heiko Carstens <heiko.carstens@...ibm.com>,
	"Luck, Tony" <tony.luck@...el.com>, Jason Baron <jbaron@...hat.com>
Subject: Re: [PATCH] tracing: Cleanup the convoluted softirq tracepoints

On 10/19/2010 03:41 PM, Mathieu Desnoyers wrote:
>>
>> OK, first of all, there are some serious WTFs here:
>>
>> # define JUMP_LABEL_INITIAL_NOP ".byte 0xe9 \n\t .long 0\n\t"
>>
>> A jump instruction is one of the worst possible NOPs.  Why are we doing
>> this?
> 
> This code is dynamically patched at boot time (and module load time) with a
> better nop, just like the function tracer does.
> 

That's just ridiculous... start out with something sane and you at least
have the chance of not having to patch it.

> Intel's manual "Intel 64 and IA-32 Architectures Optimization Reference Manual"
> 
> http://www.intel.com/Assets/PDF/manual/248966.pdf
> 
> Page C-33 (or 577 in the pdf)
> 
> "7. Selection of conditional jump instructions should be based on the
>     recommendation of section Section 3.4.1, “Branch Prediction Optimization,” to
>     improve the predictability of branches. When branches are predicted
>     successfully, the latency of jcc is effectively zero."
> 
> So it mentions "jcc", but not jmp. Is there any reason for jmp to have a higher
> latency than jcc ?
> 
> In this manual, the latency of predicted jcc is therefore 0 cycle, and its
> throughput is 0.5 cycle/insn.
> 
> NOP (page C-29) is stated to have a latency of 0.5 to 1 cycle/insn (depending on
> the exact HW), and throughput of 0.5 cycle/insn.
> 
> However, I have not found "jmp" explicitly in this listing.
> 
> So if we were executing tracepoints in a maze of jumps, we could argue that
> instruction throughput is the most important there. However, if we expect the
> common case to be surrounded by some non-ALU instructions, latency tends to
> become the most important criterion.
> 
> But I feel I might be missing something important that distinguish "jcc" from
> "jmp".

NOP has a latency of 0.5-1.0 cycle/insns, *but has no consumers*.

JMP/Jcc does have a consumer -- the IP -- and actually measuring shows
that it is much, much worse than NOP and other dummy instructions.

	-hpa
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