linux-kernel - Re: [PATCH v2 8/9] MIPS: Honor L2 bypass bit

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Message-ID: <AANLkTinJ4wU30AaBhcvJRLZ_iw-eo9tEkds8QA1S=Nqw@mail.gmail.com>
Date:	Thu, 21 Oct 2010 09:25:59 -0700
From:	Kevin Cernekee <cernekee@...il.com>
To:	Ralf Baechle <ralf@...ux-mips.org>
Cc:	linux-mips@...ux-mips.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 8/9] MIPS: Honor L2 bypass bit

On Thu, Oct 21, 2010 at 5:58 AM, Ralf Baechle <ralf@...ux-mips.org> wrote:
> I did a bit of research in the meantime.  Turns out that some MIPS
> customers are using their own L2 cache controller.  That means a simple
> check by the CPU PrID is not sufficient and we will need some sort of
> platform-specific probe, sigh.

FWIW, I did check the software user's manual for each of the four
processors in the list and verified that L2B is at CONFIG2 bit 12.  It
would be very rude for an L2 designer to redefine those bits in
defiance of the SUM, no?

I also rechecked 24KE just now, and found that L2B is defined in the
latest rev of the SUM, but in my local copy (Revision 01.02) bit 12 is
the MSB of SS instead.  Hmmm.
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