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Date: Thu, 21 Oct 2010 17:50:21 -0400 From: Andev <debiandev@...il.com> To: Sitsofe Wheeler <sitsofe@...oo.com> Cc: linux kernel <kernelnewbies@...linux.org>, LKML <linux-kernel@...r.kernel.org> Subject: Re: Disable L1/L2/L3 cache and MTRR On Thu, Oct 21, 2010 at 4:23 PM, Sitsofe Wheeler <sitsofe@...oo.com> wrote: >> Now when I run some sample benchmarks they show a slowdown of almost 1000x!! >> >> This is not reasonable since the max. The slowdown I was expecting is 200x >> considering that it will take 200 cycles to read from DRAM. > > Assuming the cache was completely disabled, won't the impact be > cumulative? E.g. imagine a memory read takes one cycle from cache and > 100 from main memory. If you read 5 instructions from cache that will > take 5 cycles. If you read 5 instructions from main memory that will be > 5*100 so 500 cycles. If it is 10 instructions then it is 10 vs 1000 and > so on... > > Are you searching for an improvement in determinism? Yes, if that was so, the slowdown is still 100x. In my test case, I removed all the entries from /proc/mtrr and also disabled L1/L2/L3 caches. When I run a benchmark which runs for 4 sec with cache, it takes almost 3000 secs without cache. I think I am messing up the /proc/mtrr file. Regards, Andev. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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