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Message-ID: <m2eib2uryc.fsf@gmail.com>
Date:	Wed, 03 Nov 2010 20:28:59 +0100
From:	Francis Moreau <francis.moro@...il.com>
To:	linux-kernel@...r.kernel.org
Subject: perf tools miscellaneous questions

Hello,

I'm trying to use perf-tools and also to learn some internals about
them. So I prefer to ask all of them in one email.

The first one is about the list of pre-defined events given by
perf-list. I couldn't find any documentations that describes these
events so excuse me if the question is stupid.

What's the difference between 'cpu-clock' and 'task-clock' event ?

What's exactly the 'cache-misses' event ? does it include both instructions
_and_ data cache misses ? both L1 and L2 caches ?

I was expecting so but the following command makes me wondering:

  $ perf stat -e cache-misses:u,l1d-loads-misses:u true
    Performance counter stats for 'true':

                763  cache-misses            
                874  L1-dcache-load-misses   

        0.000916609  seconds time elapsed

Here cache-misses < L1-dcache-load-misses.

The last question is about the source code annotation done by
perf-report. I'm using it to locate the place in my code that generates
the most data cache miss events. I can read this during a perf-report
session:

   [...]
    0.00 :           df215:       c3                      retq
    0.00 :           df216:       66 2e 0f 1f 84 00 00    nopw   %cs:0x0(%rax,%rax,1)
    0.00 :           df21d:       00 00 00
   10.00 :           df220:       48 8b 75 00             mov    0x0(%rbp),%rsi
   80.00 :           df224:       48 89 df                mov    %rbx,%rdi
    0.00 :           df227:       41 ff d4                callq  *%r12
    0.00 :           df22a:       85 c0                   test   %eax,%eax
   [...]

If I read the output correctly, most of the dcache misses are coming from
'mov %rbx, %rdi', and AFAIK this intruction can't generate any dcache
miss. What am I missing ?

Thanks.
-- 
Francis
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