linux-kernel - Re: [Security] [PATCH v3 0/4] x86: clear XD

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Date:	Thu, 11 Nov 2010 16:15:20 +0100
From:	Rogier Wolff <R.E.Wolff@...Wizard.nl>
To:	Kees Cook <kees.cook@...onical.com>
Cc:	Alan Cox <alan@...rguk.ukuu.org.uk>, x86@...nel.org,
	linux-kernel@...r.kernel.org
Subject: Re: [Security] [PATCH v3 0/4] x86: clear XD_DISABLED flag on Intel to regain NX

On Tue, Nov 09, 2010 at 05:10:39PM -0800, Kees Cook wrote:
> AG29. #GP Fault is Not Generated on Writing IA32_MISC_ENABLE [34]
>       When Execute Disable (XD) is Not Supported
> Problem: A #GP fault is not generated on writing to IA32_MISC_ENABLE [34]
>          bit in a processor which does not support Execute Disable (XD)
>          functionality.
> Implication: Writing to IA32_MISC_ENABLE [34] bit is silently ignored
>              without generating a fault.
> Workaround: None identified.
> Status: For the steppings affected, see the Summary Tables of Changes.
 
> But this case is already handled (and doesn't matter) because my
> patch already avoids this (we only clear IA32_MISC_ENABLE, not set
> it).

Ehhh. A Virtual machine monitor may need to be notified of your
"clearing" that bit. The erratum is correctly worded as for "writing"
not "setting".

But that bug is intel's problem. Not yours. 

	Roger. 

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