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Date: Thu, 11 Nov 2010 19:42:03 +0100
From: Andi Kleen <ak@...ux.intel.com>
To: Stephane Eranian <eranian@...gle.com>
CC: Andi Kleen <andi@...stfloor.org>, linux-kernel@...r.kernel.org,
fweisbec@...il.com, a.p.zijlstra@...llo.nl, mingo@...e.hu,
acme@...hat.com
Subject: Re: [PATCH 1/3] perf-events: Add support for supplementary event
registers
On 11/11/2010 7:06 PM, Stephane Eranian wrote:
Thanks for the review.
> One thing I noticed in your patch is that you don't special
> case the configuration where HT is off. In that case, the
> sharing problem goes away. I think you could override
> either way during init.
The allocator should handle that transparently. With HT off the resource is
always free. Or do you see any concrete problems with the current code path?
> Some more tidbits:
> - OFFCORE_RESPONSE_0 is 0x01b7
> - OFFCORE_RESPONSE_1 is 0x01bb
>
> The umask is not zero but 1. Dont' know if you get
> something meaningful is you pass a umask of zero.
Hmm I seem to get events that look meaningful with 0. But you're right 1
is better. I used that in manual tests, but it wasn't in the cache number
mappings. I'll fix that for the next version.
-Andi
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