| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <1289619000-13167-2-git-send-email-stepanm@codeaurora.org> Date: Fri, 12 Nov 2010 19:29:47 -0800 From: Stepan Moskovchenko <stepanm@...eaurora.org> To: dwalker@...eaurora.org Cc: davidb@...eaurora.org, bryanh@...eaurora.org, linux-arm-msm@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org, Stepan Moskovchenko <stepanm@...eaurora.org> Subject: [PATCH 01/14] msm: iommu: Increase maximum MID size to 5 bits On msm8x60, the MID field on the AXI connection to the IOMMU can be up to five bits wide. Thus, allow the IOMMU context platform data to map up to 32 MIDs. Signed-off-by: Stepan Moskovchenko <stepanm@...eaurora.org> --- arch/arm/mach-msm/include/mach/iommu.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-msm/include/mach/iommu.h b/arch/arm/mach-msm/include/mach/iommu.h index 218ef57..17fc79f 100644 --- a/arch/arm/mach-msm/include/mach/iommu.h +++ b/arch/arm/mach-msm/include/mach/iommu.h @@ -26,7 +26,7 @@ * be present. These mappings are typically determined at design time and are * not expected to change at run time. */ -#define MAX_NUM_MIDS 16 +#define MAX_NUM_MIDS 32 /** * struct msm_iommu_dev - a single IOMMU hardware instance -- 1.7.0.2 Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Powered by blists - more mailing lists