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Message-ID: <AANLkTinjpsGyZ-j9Pw2y=2YA8++HxHymbKUNcKgwssra@mail.gmail.com>
Date:	Mon, 15 Nov 2010 12:18:19 +0100
From:	Stephane Eranian <eranian@...gle.com>
To:	Peter Zijlstra <a.p.zijlstra@...llo.nl>
Cc:	Andi Kleen <andi@...stfloor.org>, linux-kernel@...r.kernel.org,
	cjashfor@...ux.vnet.ibm.com, mingo@...e.hu, fweisbec@...il.com,
	Andi Kleen <ak@...ux.intel.com>
Subject: Re: [PATCH 1/2] perf-events: Add support for supplementary event
 registers v2

On Mon, Nov 15, 2010 at 12:06 PM, Peter Zijlstra <a.p.zijlstra@...llo.nl> wrote:
> On Mon, 2010-11-15 at 12:01 +0100, Stephane Eranian wrote:
>> On Sat, Nov 13, 2010 at 11:32 AM, Peter Zijlstra <a.p.zijlstra@...llo.nl> wrote:
>> > On Sat, 2010-11-13 at 11:13 +0100, Andi Kleen wrote:
>> >> > Hrmm,. this doesn't really scale right wrt multiple extra_regs.
>> >> >
>> >> > You made the extra_regs thing fairly extensible, but the above doesn't
>> >> > really work well if there's multiple extra regs (say OFFCORE and
>> >> > LBR_CONFIG -- possibly even the two OFFCORE regs present on westmere).
>> >> >
>> >> > It basically needs a per-core state for each extra_reg possible.
>> >>
>> >> It shouldn't be too hard to extend it to use a table. I didn't want
>> >> to do that for the first iteration. I guess it could be done as followons
>> >> once LBR is implemented.
>> >
>> > Isn't it also relevant for the two offcore regs for wsm?
>> >
>> But that's two distinct events (0xbb and 0xb7), though they behave
>> exactly the same and have the same set of umasks and extra MSR
>> values.
>
> Ah, my bad, I thought there were two separate msrs, ok I'll take a last
> look at these patches and if nothing else pops out I'll take them.
>
OFFCORE_RESPONSE_0, event code 0xb7 -> extra MSR@...a6
OFFCORE_REPPONSE_1, event code 0xbb -> extra MSR@...a7

Why would you want to measure both at the same time?
Because you can measure two distinct request/response in one run.

If you want to measure both you need to create two distinct perf events.
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