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Date: Thu, 18 Nov 2010 11:47:32 +0100 From: Andi Kleen <andi@...stfloor.org> To: a.p.zijlstra@...llo.nl Cc: eranian@...gle.com, linux-kernel@...r.kernel.org, x86@...nel.org, Andi Kleen <ak@...ux.intel.com> Subject: [PATCH 2/4] perf: Document enhanced event encoding for OFFCORE_MSR From: Andi Kleen <ak@...ux.intel.com> Signed-off-by: Andi Kleen <ak@...ux.intel.com> --- tools/perf/Documentation/perf-list.txt | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/tools/perf/Documentation/perf-list.txt b/tools/perf/Documentation/perf-list.txt index 399751b..700afd7 100644 --- a/tools/perf/Documentation/perf-list.txt +++ b/tools/perf/Documentation/perf-list.txt @@ -58,6 +58,13 @@ raw encoding of 0x1A8 can be used: perf stat -e r1a8 -a sleep 1 perf record -e r1a8 ... +Some special events on x86 encode additional data in the normally unused +[32;63] bits of the raw value. This is particularly used for +the OFFCORE_RESPONSE events on Intel Core i7. The 16bit +mask in the OFFCORE_RESPONSE register is put into bits [32;48]. +For example the OFFCORE_RESPONSE_0.ANY_DATA.ANY_CACHE_DRAM event +is encoded as r00007f11004301b7. + You should refer to the processor specific documentation for getting these details. Some of them are referenced in the SEE ALSO section below. -- 1.7.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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