linux-kernel - Re: [RFC PATCH 2/3 v2] perf: Implement Nehalem uncore pmu

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Message-ID: <1291173711.2405.223.camel@minggr.sh.intel.com>
Date:	Wed, 01 Dec 2010 11:21:51 +0800
From:	Lin Ming <ming.m.lin@...el.com>
To:	Stephane Eranian <eranian@...gle.com>
Cc:	Don Zickus <dzickus@...hat.com>,
	Peter Zijlstra <a.p.zijlstra@...llo.nl>,
	Ingo Molnar <mingo@...e.hu>, Andi Kleen <andi@...stfloor.org>,
	lkml <linux-kernel@...r.kernel.org>,
	Frederic Weisbecker <fweisbec@...il.com>,
	Arjan van de Ven <arjan@...radead.org>
Subject: Re: [RFC PATCH 2/3 v2] perf: Implement Nehalem uncore pmu

On Fri, 2010-11-26 at 18:06 +0800, Stephane Eranian wrote:
> On Fri, Nov 26, 2010 at 10:00 AM, Lin Ming <lin@...g.vg> wrote:
> > On Fri, Nov 26, 2010 at 4:33 PM, Stephane Eranian <eranian@...gle.com> wrote:
> >> Lin,
> >>
> >> Looked at the perfmon code, and it seems the mask is actual
> >> cores, not threads:
> >>                rdmsrl(MSR_NHM_UNC_GLOBAL_CTRL, val);
> >>                val |= 1ULL << (48 + cpu_data(smp_processor_id()).cpu_core_id);
> >>                wrmsrl(MSR_NHM_UNC_GLOBAL_CTRL, val);
> >>
> >> That seems to imply both threads will get the interrupt.
> >>
> >> In the the overflowed event was programmed from on of the two threads, that
> >> means one will process the overflow, the other will get spurious.
> >>
> >> On the cores where no uncore was programmed, then both threads will have
> >> a spurious interrupt.
> >
> > But in my test, if HT is on, only the 2 theads in one of the four cores
> > will receive the interrupt. Even worse, we don't know which core will
> > receive the interrupt
> > when overflow happens.
> >
> The MSR_NHM_UNC_GLOBAL_CTRL is per socket not per core.

Understood.

> 
> > I'll do more tests to verify this.
> 
> In your tests, are your programming the same uncore event
> across all CPUs? If so then you may have a race condition
> setting the MSR because it read-modify-write.
> 
> What about you program only one uncore event from one CPU?

This is what I tested, programming only one uncore event from one CPU.
When HT is off, all four cores in the socket receive the interrupt.
When HT is on, only the 2 threads in one of the four cores receive the
interrupt.

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