linux-kernel - Re: [PATCH 3/5] msm: timer: SMP timer support for msm

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Date:	Mon, 6 Dec 2010 10:20:46 +0000
From:	Russell King - ARM Linux <linux@....linux.org.uk>
To:	Thomas Gleixner <tglx@...utronix.de>
Cc:	Jeff Ohlstein <johlstei@...eaurora.org>,
	Daniel Walker <dwalker@...eaurora.org>,
	linux-arm-msm@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org,
	LKML <linux-kernel@...r.kernel.org>,
	Brian Swetland <swetland@...gle.com>,
	Dima Zavin <dima@...roid.com>, arve@...roid.com,
	David Brown <davidb@...eaurora.org>,
	Bryan Huntsman <bryanh@...eaurora.org>,
	Stepan Moskovchenko <stepanm@...eaurora.org>,
	Gregory Bean <gbean@...eaurora.org>,
	Steve Muckle <smuckle@...eaurora.org>
Subject: Re: [PATCH 3/5] msm: timer: SMP timer support for msm

On Mon, Dec 06, 2010 at 10:56:14AM +0100, Thomas Gleixner wrote:
> > +	local_irq_save(flags);
> > +	get_irq_chip(clock->irq.irq)->unmask(clock->irq.irq);
> 
> Why are you fiddling wiht the irqchip functions directly ? Please use
> disable_irq/enable_irq if at all.

PPI.  The interrupt has to be enabled by the very same CPU that wants
to receive the interrupt.  Other CPUs on the system do not have access
to the interrupt enable bits for PPIs.

That's something which genirq can't handle because it doesn't _actually_
support real per-CPU interrupts - iow, ones which are truely private to
CPU N.

Eg, if IRQ 29 is the local timer interrupt, then CPU0 has its own IRQ29
which is distinctly different - and has separate enable registers and
ultimately different timer hardware - from CPU1's IRQ29.

On the other SMP platforms, these interrupts aren't handled by genirq,
but we do control them via code like the above (which I'm about to kill
off and move that detail into gic.c.)
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