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Date: Mon, 13 Dec 2010 00:46:49 +0100 (CET)
From: Andi Kleen <andi@...stfloor.org>
To: axel.lin@...il.com, lrg@...mlogic.co.uk,
broonie@...nsource.wolfsonmicro.com, gregkh@...e.de,
ak@...ux.intel.com, linux-kernel@...r.kernel.org, stable@...nel.org
Subject: [PATCH] [109/223] ASoC: wm8961 - clear WM8961_MCLKDIV bit for freq <= 16500000
2.6.35-longterm review patch. If anyone has any objections, please let me know.
------------------
From: Axel Lin <axel.lin@...il.com>
commit 2f7dceeda4708f470fd927adb3861bd8ebbe2310 upstream.
MCLKDIV bit of Register 04h Clocking1:
0 : Divide by 1
1 : Divide by 2
Thus in the case of freq <= 16500000, we should clear MCLKDIV bit.
Signed-off-by: Axel Lin <axel.lin@...il.com>
Acked-by: Liam Girdwood <lrg@...mlogic.co.uk>
Signed-off-by: Mark Brown <broonie@...nsource.wolfsonmicro.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@...e.de>
Signed-off-by: Andi Kleen <ak@...ux.intel.com>
---
sound/soc/codecs/wm8961.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Index: linux/sound/soc/codecs/wm8961.c
===================================================================
--- linux.orig/sound/soc/codecs/wm8961.c
+++ linux/sound/soc/codecs/wm8961.c
@@ -736,7 +736,7 @@ static int wm8961_set_sysclk(struct snd_
freq /= 2;
} else {
dev_dbg(codec->dev, "Using MCLK/1 for %dHz MCLK\n", freq);
- reg &= WM8961_MCLKDIV;
+ reg &= ~WM8961_MCLKDIV;
}
snd_soc_write(codec, WM8961_CLOCKING1, reg);
--
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