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Message-ID: <AANLkTi=LZJiEP2rfQ_gL096A1GbCW+FBBmfG2eSdFY5W@mail.gmail.com>
Date: Mon, 13 Dec 2010 14:56:04 +0000
From: Catalin Marinas <catalin.marinas@....com>
To: ykaoua@...lcomm.com
Cc: David Brown <davidb@...eaurora.org>,
Daniel Walker <dwalker@...eaurora.org>,
Russell King <linux@....linux.org.uk>,
linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
Dima Zavin <dima@...roid.com>,
Arve Hjønnevåg <arve@...roid.com>,
Steve Muckle <smuckle@...eaurora.org>,
Jeff Ohlstein <johlstei@...eaurora.org>,
Brian Swetland <swetland@...gle.com>,
Bryan Huntsman <bryanh@...eaurora.org>,
linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v3 5/5] msm: add SMP support for msm
On 13 December 2010 01:20, <ykaoua@...lcomm.com> wrote:
> --- /dev/null
> +++ b/arch/arm/mach-msm/headsmp.S
[...]
> +ENTRY(msm_secondary_startup)
> + mrc p15, 0, r0, c0, c0, 5 @ MPIDR
> + and r0, r0, #15 @ What CPU am I
> + adr r4, 1f @ address of
> + ldmia r4, {r5, r6} @ load curr addr and pen_rel addr
> + sub r4, r4, r5 @ determine virtual/phys offsets
> + add r6, r6, r4 @ apply
> +pen:
> + wfe
> + dsb @ ensure subsequent access is
> + @ after event
> +
> + ldr r7, [r6] @ pen_rel has cpu to remove from reset
> + cmp r7, r0 @ are we lucky?
> + bne pen
Is the primary CPU using SEV to wake the secondary from the WFE? I may
have missed it.
--
Catalin
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