linux-kernel - Re: [PATCHv8 00/12] Contiguous Memory Allocator

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Message-ID: <20101223142053.GN3636@n2100.arm.linux.org.uk>
Date:	Thu, 23 Dec 2010 14:20:53 +0000
From:	Russell King - ARM Linux <linux@....linux.org.uk>
To:	Tomasz Fujak <t.fujak@...sung.com>
Cc:	Michal Nazarewicz <mina86@...a86.com>,
	Kyungmin Park <kmpark@...radead.org>,
	linux-arm-kernel@...ts.infradead.org,
	Daniel Walker <dwalker@...eaurora.org>,
	Johan MOSSBERG <johan.xx.mossberg@...ricsson.com>,
	Mel Gorman <mel@....ul.ie>, linux-kernel@...r.kernel.org,
	linux-mm@...ck.org, Ankita Garg <ankita@...ibm.com>,
	Andrew Morton <akpm@...ux-foundation.org>,
	linux-media@...r.kernel.org,
	KAMEZAWA Hiroyuki <kamezawa.hiroyu@...fujitsu.com>,
	Marek Szyprowski <m.szyprowski@...sung.com>
Subject: Re: [PATCHv8 00/12] Contiguous Memory Allocator

On Thu, Dec 23, 2010 at 03:08:21PM +0100, Tomasz Fujak wrote:
> On 2010-12-23 14:51, Russell King - ARM Linux wrote:
> > On Thu, Dec 23, 2010 at 02:41:26PM +0100, Michal Nazarewicz wrote:
> >> Russell King - ARM Linux <linux@....linux.org.uk> writes:
> >>> Has anyone addressed my issue with it that this is wide-open for
> >>> abuse by allocating large chunks of memory, and then remapping
> >>> them in some way with different attributes, thereby violating the
> >>> ARM architecture specification?
> >>>
> >>> In other words, do we _actually_ have a use for this which doesn't
> >>> involve doing something like allocating 32MB of memory from it,
> >>> remapping it so that it's DMA coherent, and then performing DMA
> >>> on the resulting buffer?
> >> Huge pages.
> >>
> >> Also, don't treat it as coherent memory and just flush/clear/invalidate
> >> cache before and after each DMA transaction.  I never understood what's
> >> wrong with that approach.
> > If you've ever used an ARM system with a VIVT cache, you'll know what's
> > wrong with this approach.
> >
> > ARM systems with VIVT caches have extremely poor task switching
> > performance because they flush the entire data cache at every task switch
> > - to the extent that it makes system performance drop dramatically when
> > they become loaded.
> >
> > Doing that for every DMA operation will kill the advantage we've gained
> > from having VIPT caches and ASIDs stone dead.
> This statement effectively means: don't map dma-able memory to the CPU
> unless it's uncached. Have I missed anything?

I'll give you another solution to the problem - lobby ARM Ltd to have
this restriction lifted from the architecture specification, which
will probably result in the speculative prefetching also having to be
removed.

That would be my preferred solution if I had the power to do so, but
I have to live with what ARM Ltd (and their partners such as yourselves)
decide should end up in the architecture specification.
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