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Date: Mon, 10 Jan 2011 12:43:29 -0500 (EST) From: Len Brown <lenb@...nel.org> To: Thomas Gleixner <tglx@...utronix.de> Cc: Peter Zijlstra <peterz@...radead.org>, Rob <roblinux@...il.com>, linux-kernel@...r.kernel.org Subject: Re: TSC as clocksource > > On Mon, 2011-01-10 at 09:54 +1100, Rob wrote: > > > Want to use TSC as clocksource > > > have a Intel Core2 Duo with constant_tsc flag > > > TSC should be stable at C1 + C2, it is debatable whether C3 is stable no debate, TSC on Core2 stops in C3. > > > Using processor.max_cstate=2 to use only C1 + C2 changes nothing, still get > > > Monitor-Mwait will be used to enter C-3 state > > > there should be checks before this is forced > > We unconditinally set TSC unstable for anything > C1. The reason is > that we had a lot of troubles with BIOSes which advertise C2, but in > fact implement C3. Unfortunately we can't verify that. Right. There are some Core2 where what ACPI advertises as C2 the TSC works, and some where it does something other than "hardware C2", such as "hardware C3" and the TSC stops, so Linux is conservative here. If you want a stable TSC on Core2 (and before) then you need to use either idle=poll or processor.max_cstate=1. Nehalem and newer (Core i7 etc) have an invarient TSC that works no matter what C-states are present. cheers, Len Brown, Intel Open Source Technology Center -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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