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Message-Id: <1295854549-7928-6-git-send-email-dengcheng.zhu@gmail.com>
Date: Mon, 24 Jan 2011 15:35:49 +0800
From: Deng-Cheng Zhu <dengcheng.zhu@...il.com>
To: ralf@...ux-mips.org, a.p.zijlstra@...llo.nl, fweisbec@...il.com,
will.deacon@....com
Cc: linux-mips@...ux-mips.org, linux-kernel@...r.kernel.org,
wuzhangjin@...il.com, paulus@...ba.org, mingo@...e.hu,
acme@...hat.com, dengcheng.zhu@...il.com, matt@...sole-pimps.org,
sshtylyov@...sta.com, ddaney@...iumnetworks.com
Subject: [RESEND PATCH v4 5/5] MIPS/Perf-events: Use unsigned delta for right shift in event update
Leverage the commit for ARM by Will Deacon:
- 446a5a8b1eb91a6990e5c8fe29f14e7a95b69132
ARM: 6205/1: perf: ensure counter delta is treated as unsigned
Hardware performance counters on ARM are 32-bits wide but atomic64_t
variables are used to represent counter data in the hw_perf_event structure.
The armpmu_event_update function right-shifts a signed 64-bit delta variable
and adds the result to the event count. This can lead to shifting in sign-bits
if the MSB of the 32-bit counter value is set. This results in perf output
such as:
Performance counter stats for 'sleep 20':
18446744073460670464 cycles <-- 0xFFFFFFFFF12A6000
7783773 instructions # 0.000 IPC
465 context-switches
161 page-faults
1172393 branches
20.154242147 seconds time elapsed
This patch ensures that the delta value is treated as unsigned so that the
right shift sets the upper bits to zero.
Acked-by: Will Deacon <will.deacon@....com>
Acked-by: David Daney <ddaney@...iumnetworks.com>
Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@...il.com>
---
Changes:
v4 - v3:
o None
v3 - v2:
o Keep all mentioned commits in the form of number + title + original
summary + (MIPS specific info when needed).
v2 - v1:
o None
arch/mips/kernel/perf_event.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/mips/kernel/perf_event.c b/arch/mips/kernel/perf_event.c
index 8f7d2f8..a824485 100644
--- a/arch/mips/kernel/perf_event.c
+++ b/arch/mips/kernel/perf_event.c
@@ -169,7 +169,7 @@ static void mipspmu_event_update(struct perf_event *event,
unsigned long flags;
int shift = 64 - TOTAL_BITS;
s64 prev_raw_count, new_raw_count;
- s64 delta;
+ u64 delta;
again:
prev_raw_count = local64_read(&hwc->prev_count);
--
1.7.1
--
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