linux-kernel - Re: [PATCH v2 04/28] ARM: mm: cache-l2x0: Add support for re-enabling l2x0

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <1295968464.10109.264.camel@e102109-lin.cambridge.arm.com>
Date:	Tue, 25 Jan 2011 15:14:24 +0000
From:	Catalin Marinas <catalin.marinas@....com>
To:	Colin Cross <ccross@...roid.com>
Cc:	linux-tegra@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
	olof@...om.net, konkers@...roid.com,
	Russell King <linux@....linux.org.uk>,
	Santosh Shilimkar <santosh.shilimkar@...com>,
	Linus Walleij <linus.walleij@...ricsson.com>,
	Tony Lindgren <tony@...mide.com>, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 04/28] ARM: mm: cache-l2x0: Add support for
 re-enabling l2x0

On Mon, 2011-01-24 at 02:01 +0000, Colin Cross wrote:
> --- a/arch/arm/mm/cache-l2x0.c
> +++ b/arch/arm/mm/cache-l2x0.c
> @@ -252,16 +252,26 @@ static void l2x0_flush_range(unsigned long start, unsigned long end)
>         spin_unlock_irqrestore(&l2x0_lock, flags);
>  }
> 
> +/* enables l2x0 after l2x0_disable, does not invalidate */
> +void l2x0_enable(void)
> +{
> +       unsigned long flags;
> +
> +       spin_lock_irqsave(&l2x0_lock, flags);
> +       writel_relaxed(1, l2x0_base + L2X0_CTRL);
> +       spin_unlock_irqrestore(&l2x0_lock, flags);
> +}
> +
>  static void l2x0_disable(void)
>  {
>         unsigned long flags;
> 
>         spin_lock_irqsave(&l2x0_lock, flags);
> -       writel(0, l2x0_base + L2X0_CTRL);
> +       writel_relaxed(0, l2x0_base + L2X0_CTRL);
>         spin_unlock_irqrestore(&l2x0_lock, flags);
>  }
> 
> -void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
> +void l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
>  {
>         __u32 aux;
>         __u32 cache_id;

So this assumes that the L2 registers are accessible. I suspect the
platform code calling it should know this.

The patch looks fine.

Acked-by: Catalin Marinas <catalin.marinas@....com>


--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/