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Message-ID: <AANLkTinknGa1WZ-kxFNG6pZOaJHgF_tkdz6aAjsLf6bM@mail.gmail.com>
Date: Mon, 7 Feb 2011 15:59:32 -0600
From: Stuart Hayes <stuart.w.hayes@...il.com>
To: linux-kernel@...r.kernel.org, douglas_warzecha@...l.com,
shyam_iyer@...l.com
Subject: [RESEND PATCH] dcdbas: force SMI to happen when expected
Resending from a different email address so I don't have to attach the
patch as a file.
The dcdbas driver can do an I/O write to cause a SMI to occur. On some sys=
tems I/O writes are posted in the chipset and don't complete immediately. =
This can result in the SMI happening at a later time. This can result in r=
andom failures since the SMI handler expects the EBX register to contain a =
pointer, and the handler can write to memory.
Performing an I/O read to the same address as the I/O write will force the =
I/O write to complete. The patch is against the 2.6.37 kernel and has been=
tested.
Signed-off-by: Stuart Hayes <stuart.w.hayes@...il.com>
Acked-by: Doug Warzecha <douglas_warzecha@...l.com>
---
diff -purN linux-2.6.37/drivers/firmware/dcdbas.c
linux-2.6.37_test/drivers/firmware/dcdbas.c
--- linux-2.6.37/drivers/firmware/dcdbas.c 2011-01-18
10:44:44.869882461 -0500
+++ linux-2.6.37_test/drivers/firmware/dcdbas.c 2011-01-18
10:41:15.404612154 -0500
@@ -278,6 +278,9 @@ int dcdbas_smi_request(struct smi_cmd *s
: "memory"
);
+ /* read to force posted write through and make SMI happen now */
+ inb(smi_cmd->command_address);
+
out:
set_cpus_allowed_ptr(current, old_mask);
free_cpumask_var(old_mask);
--
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