linux-kernel - Re: [PATCH 0/2] jump label: 2.6.38 updates

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Message-ID: <AANLkTinbGYo=mLgseXTR-k1Cns+GFBGPm0VXVgtS02L0@mail.gmail.com>
Date:	Thu, 17 Feb 2011 10:55:25 +0000
From:	Will Newton <will.newton@...il.com>
To:	Will Simoneau <simoneau@....uri.edu>
Cc:	Steven Rostedt <rostedt@...dmis.org>,
	David Miller <davem@...emloft.net>, hpa@...or.com,
	matt@...sole-pimps.org, peterz@...radead.org, jbaron@...hat.com,
	mathieu.desnoyers@...ymtl.ca, mingo@...e.hu, tglx@...utronix.de,
	roland@...hat.com, rth@...hat.com, masami.hiramatsu.pt@...achi.com,
	fweisbec@...il.com, avi@...hat.com, sam@...nborg.org,
	ddaney@...iumnetworks.com, michael@...erman.id.au,
	linux-kernel@...r.kernel.org, vapier@...too.org,
	cmetcalf@...era.com, dhowells@...hat.com, schwidefsky@...ibm.com,
	heiko.carstens@...ibm.com, benh@...nel.crashing.org
Subject: Re: [PATCH 0/2] jump label: 2.6.38 updates

On Wed, Feb 16, 2011 at 10:51 PM, Will Simoneau <simoneau@....uri.edu> wrote:
> On 12:41 Wed 16 Feb     , Will Newton wrote:
>> On Wed, Feb 16, 2011 at 12:18 PM, Steven Rostedt <rostedt@...dmis.org> wrote:
>> > I'm curious, how is cmpxchg() implemented on this architecture? As there
>> > are several places in the kernel that uses this on regular variables
>> > without any "accessor" functions.
>>
>> We can invalidate the cache manually. The current cpu will see the new
>> value (post-cache invalidate) and the other cpus will see either the
>> old value or the new value depending on whether they read before or
>> after the invalidate, which is racy but I don't think it is
>> problematic. Unless I'm missing something...
>
> If I understand this correctly, the manual invalidates must propagate to
> all CPUs that potentially read the value, even if there is no
> contention. Doesn't this involve IPIs? How does it not suck?

The cache is shared between cores (in that regard it's more like a
hyper-threaded core than a true multi-core) so is completely coherent,
so this is the one bit that doesn't really suck! Having spoken to our
hardware guys I'm confident that we'll only ever build a handful of
chip designs with the current way of doing ll/sc and hopefully future
cores will do this the "right" way.
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