linux-kernel - Re: [PATCH 4/4] msm: scm: Get cacheline size from CTR

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Date:	Thu, 24 Feb 2011 22:32:06 +0300
From:	Sergei Shtylyov <sshtylyov@...sta.com>
To:	Stephen Boyd <sboyd@...eaurora.org>
CC:	David Brown <davidb@...eaurora.org>, linux-arm-msm@...r.kernel.org,
	linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH 4/4] msm: scm: Get cacheline size from CTR

Hello.

Stephen Boyd wrote:

> Instead of hardcoding the cacheline size as 32, get the cacheline
> size from the CTR register.

> Signed-off-by: Stephen Boyd <sboyd@...eaurora.org>
> ---
>  arch/arm/mach-msm/scm.c |   17 ++++++++++++-----
>  1 files changed, 12 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/mach-msm/scm.c b/arch/arm/mach-msm/scm.c
> index cfa808d..0528c71 100644
> --- a/arch/arm/mach-msm/scm.c
> +++ b/arch/arm/mach-msm/scm.c
[...]
> @@ -207,6 +204,14 @@ static int __scm_call(const struct scm_command *cmd)
>  	return ret;
>  }
>  
> +static inline u32 dcache_line_size(void)
> +{
> +	u32 ctr;
> +
> +	asm volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr));
> +	return 4 << ((ctr >> 16) & 0xf);
> +}

    Won't generic cache_line_size() macro do instead? It's defined as 
L1_CACHE_BYTES.

WBR, Sergei
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