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Message-ID: <20110228090833.GA7439@elte.hu>
Date: Mon, 28 Feb 2011 10:08:33 +0100
From: Ingo Molnar <mingo@...e.hu>
To: Lin Ming <ming.m.lin@...el.com>
Cc: Stephane Eranian <eranian@...gle.com>,
Peter Zijlstra <a.p.zijlstra@...llo.nl>,
Andi Kleen <andi@...stfloor.org>,
lkml <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 -tip] perf: x86, add SandyBridge support
* Lin Ming <ming.m.lin@...el.com> wrote:
> > In other words, bit 0-3 of the umask cannot be zero.
>
> I got the umask from "Table 30-20. PEBS Performance Events for Intel
> microarchitecture code name Sandy Bridge".
>
> But from "Table A-2. Non-Architectural Performance Events In the Processor Core
> for Intel Core Processor 2xxx Series", the combinations are needed as you show
> above.
>
> Which one is correct?
Since you have access to the hardware, could you please test and see it in practice
which one is correct?
Thanks,
Ingo
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