linux-kernel - Re: [PATCH v2 -tip] perf: x86, add SandyBridge support

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Message-Id: <1298904994.2169.60.camel@localhost>
Date:	Mon, 28 Feb 2011 22:56:34 +0800
From:	Lin Ming <ming.m.lin@...el.com>
To:	Peter Zijlstra <a.p.zijlstra@...llo.nl>
Cc:	Ingo Molnar <mingo@...e.hu>, Stephane Eranian <eranian@...gle.com>,
	Andi Kleen <andi@...stfloor.org>,
	lkml <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 -tip] perf: x86, add SandyBridge support

On Mon, 2011-02-28 at 17:15 +0800, Peter Zijlstra wrote:
> On Mon, 2011-02-28 at 15:22 +0800, Lin Ming wrote:
> > This patch adds basic SandyBridge support, including hardware cache
> > events and PEBS events support.
> > 
> > LLC-* hareware cache events don't work for now, it depends on the
> > offcore patches.
> 
> What's the status of those, Stephane reported some problems last I
> remember?
> 
> 
> >  #define INTEL_EVENT_CONSTRAINT(c, n)	\
> >  	EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
> > +#define INTEL_EVENT_CONSTRAINT2(c, n)	\
> > +	EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
> 
> That's a particularly bad name, how about something like
> 
> INTEL_UEVENT_CONSTRAINT or somesuch.
> 
> > @@ -702,7 +738,13 @@ static void intel_ds_init(void)
> >  			printk(KERN_CONT "PEBS fmt1%c, ", pebs_type);
> >  			x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
> >  			x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
> > -			x86_pmu.pebs_constraints = intel_nehalem_pebs_events;
> > +			switch (boot_cpu_data.x86_model) {
> > +			case 42: /* SandyBridge */
> > +				x86_pmu.pebs_constraints = intel_snb_pebs_events;
> > +				break;
> > +			default:
> > +				x86_pmu.pebs_constraints = intel_nehalem_pebs_events;
> > +			}
> >  			break;
> >  
> >  		default:
> 
> We already have this massive model switch right after this function,
> might as well move the pebs constraint assignment there.

How about below?
Leave the default pebs constraint assignment in intel_ds_init, and
overwrite it for snb in intel_pmu_init.

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 66712dd..d6edc8a 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -1182,6 +1182,7 @@ static __init int intel_pmu_init(void)
 		intel_pmu_lbr_init_nhm();
 
 		x86_pmu.event_constraints = intel_snb_event_constraints;
+		x86_pmu.pebs_constraints = intel_snb_pebs_events;
 		pr_cont("SandyBridge events, ");
 		break;
 
diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c
index 2128755..3e5530b 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
@@ -740,13 +740,6 @@ static void intel_ds_init(void)
 			printk(KERN_CONT "PEBS fmt1%c, ", pebs_type);
 			x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
 			x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
-			switch (boot_cpu_data.x86_model) {
-			case 42: /* SandyBridge */
-				x86_pmu.pebs_constraints = intel_snb_pebs_events;
-				break;
-			default:
-				x86_pmu.pebs_constraints = intel_nehalem_pebs_events;
-			}
 			break;
 
 		default:



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