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Message-ID: <alpine.LFD.2.00.1103021026240.2701@localhost6.localdomain6>
Date:	Wed, 2 Mar 2011 10:27:34 +0100 (CET)
From:	Thomas Gleixner <tglx@...utronix.de>
To:	"TK, Pratheesh Gangadhar" <pratheesh@...com>
cc:	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"hjk@...sjkoch.de" <hjk@...sjkoch.de>,
	"gregkh@...e.de" <gregkh@...e.de>,
	"sshtylyov@...sta.com" <sshtylyov@...sta.com>,
	"arnd@...db.de" <arnd@...db.de>,
	"Chatterjee, Amit" <amit.chatterjee@...com>,
	"davinci-linux-open-source@...ux.davincidsp.com" 
	<davinci-linux-open-source@...ux.davincidsp.com>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>
Subject: RE: [PATCH v7 1/1] PRUSS UIO driver support

On Wed, 2 Mar 2011, TK, Pratheesh Gangadhar wrote:
> > From: Thomas Gleixner [mailto:tglx@...utronix.de]
> > > +	/* Disable interrupt */
> > > +	iowrite32((val & ~intr_mask), intren_reg);
> 
> I checked more on this and actually INTC h/w has Host Interrupt
> Enable Indexed Set Register (HIEISR) and Host Interrupt Enable Indexed
> Clear Register(HIEICR) which I can use to enable/disable interrupts
> without doing RMW. I will use these registers and then we don't need
> all the spinlock and irqcontrol stuff. So I need to do
> 
> iowrite32((intr_bit, HIEICR);// This disable the interrupt bit
> in intern_reg.
> 
> Userspace can use HIEISR to re-enable the interrupt.

Great, that makes it way simpler!
 
> > It's not the purpose of a review to tell you what you need to change
> > mechanically. Reviewers hint to a correct solution and you are
> > supposed to lookup what that solution means and act accordingly. If
> > you do not understand the hint or its implications please ask _before_
> > sending a new patch set.
> 
> Seriously, I went to "fix the comments" mode. Sorry about that. Anyway
> I learnt more about things by making mistakes i.e. the positive side.
> Thanks a lot for helping us improve on this. 

Welcome!


	tglx
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