linux-kernel - RE: [PATCH] omap:iommu-added cache flushing operation for L2 cache

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Message-ID: <1dc497a090414bf80ff588791d6db5cc@mail.gmail.com>
Date:	Wed, 2 Mar 2011 18:18:05 +0530
From:	Santosh Shilimkar <santosh.shilimkar@...com>
To:	Fernando Guzman Lugo <fernando.lugo@...com>, hiroshi.doyu@...ia.com
Cc:	tony@...mide.com, linux@....linux.org.uk,
	linux-omap@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
	linux-kernel@...r.kernel.org, Ramesh Gupta <grgupta@...com>,
	Hari Kanigeri <h-kanigeri2@...com>
Subject: RE: [PATCH] omap:iommu-added cache flushing operation for L2 cache

Hello,
> -----Original Message-----
> From: linux-omap-owner@...r.kernel.org [mailto:linux-omap-
> owner@...r.kernel.org] On Behalf Of Fernando Guzman Lugo
> Sent: Wednesday, March 02, 2011 1:17 AM
> To: hiroshi.doyu@...ia.com
> Cc: tony@...mide.com; linux@....linux.org.uk; linux-
> omap@...r.kernel.org; linux-arm-kernel@...ts.infradead.org; linux-
> kernel@...r.kernel.org; Ramesh Gupta; Hari Kanigeri
> Subject: [PATCH] omap:iommu-added cache flushing operation for L2
> cache
>
> From: Ramesh Gupta <grgupta@...com>
>
> Signed-off-by: Ramesh Gupta <grgupta@...com>
> Signed-off-by: Hari Kanigeri <h-kanigeri2@...com>
> ---
>  arch/arm/plat-omap/iommu.c |   22 ++++++++--------------
>  1 files changed, 8 insertions(+), 14 deletions(-)
>
> diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
> index e3eb038..aeb2c33 100644
> --- a/arch/arm/plat-omap/iommu.c
> +++ b/arch/arm/plat-omap/iommu.c
> @@ -471,22 +471,15 @@ EXPORT_SYMBOL_GPL(foreach_iommu_device);
>   */
>  static void flush_iopgd_range(u32 *first, u32 *last)
>  {
> -	/* FIXME: L2 cache should be taken care of if it exists */
> -	do {
> -		asm("mcr	p15, 0, %0, c7, c10, 1 @ flush_pgd"
> -		    : : "r" (first));
> -		first += L1_CACHE_BYTES / sizeof(*first);
> -	} while (first <= last);
> +	dmac_flush_range(first, last);

There is note just above this API.
/*
 * These are private to the dma-mapping API.  Do not use directly.
 * Their sole purpose is to ensure that data held in the cache
 * is visible to DMA, or data written by DMA to system memory is
 * visible to the CPU.
 */
#define dmac_map_area                   cpu_cache.dma_map_area
#define dmac_unmap_area         cpu_cache.dma_unmap_area
#define dmac_flush_range                cpu_cache.dma_flush_range

> +	outer_flush_range(virt_to_phys(first), virt_to_phys(last));
>  }
>
--
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