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Message-ID: <1299678879.2308.2987.camel@twins>
Date: Wed, 09 Mar 2011 14:54:39 +0100
From: Peter Zijlstra <peterz@...radead.org>
To: Martin Schwidefsky <schwidefsky@...ibm.com>
Cc: Benjamin Herrenschmidt <benh@...nel.crashing.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
linuxppc-dev <linuxppc-dev@...ts.ozlabs.org>,
Jesse Larrew <jlarrew@...ux.vnet.ibm.com>
Subject: Re: [BUG] rebuild_sched_domains considered dangerous
On Wed, 2011-03-09 at 14:46 +0100, Martin Schwidefsky wrote:
> On Wed, 09 Mar 2011 14:33:56 +0100
> Peter Zijlstra <peterz@...radead.org> wrote:
>
> > On Wed, 2011-03-09 at 14:31 +0100, Martin Schwidefsky wrote:
> > > > But if you don't also update the cpu->node memory mappings (which I
> > > > think it near impossible) what good is it to change the scheduler
> > > > topology?
> > >
> > > The memory for the different LPARs is striped over all nodes (or books as we
> > > call them). We heavily rely on the large shared cache between the books to hide
> > > the different memory access latencies.
> >
> > Right, so effectively you don't have NUMA due to that striping. So why
> > then change the CPU topology? Simply create a topology without NUMA and
> > keep it static, that accurately reflects the memory topology.
>
> Well the CPU topology can change due to different grouping of logical CPUs
> dependent on which LPARs are activated. And we effectively do not have a
> memory topology, only CPU. Its basically all about caches, we want to
> reflect the distance between CPUs over the up to 4 cache levels.
Right, so I consider caches to be part of the memory topology, anyway,
if this all is very rare then yeah, that works out.
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