linux-kernel - RE: [patch 5/5] [RFC] gpio: langwell: Clear edge bit before handling

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Message-ID: <1865303E0DED764181A9D882DEF65FB688211171FD@shsmsx502.ccr.corp.intel.com>
Date:	Fri, 18 Mar 2011 10:33:56 +0800
From:	"Du, Alek" <alek.du@...el.com>
To:	Thomas Gleixner <tglx@...utronix.de>,
	LKML <linux-kernel@...r.kernel.org>
CC:	Grant Likely <grant.likely@...retlab.ca>,
	"Tang, Feng" <feng.tang@...el.com>,
	Alan Cox <alan@...rguk.ukuu.org.uk>
Subject: RE: [patch 5/5] [RFC] gpio: langwell: Clear edge bit before handling

On Fri, 18 Mar 2011 03:32:58 +0800
Thomas Gleixner <tglx@...utronix.de> wrote:

> I don't have the specs for this beast, but it looks a lot like the PXA
> GPIO block. Though I bet it's the same IP and the driver should have
> reused the PXA code.
> 

I think so.

> Acknowleding the edge detect status after handling one or more gpio
> interrupts looks wrong. We might lose an edge which came in while we
> handled the previous one.
> 

Thanks for it. Although losing interrupt can always happen if the pending
IRQs are more than 1, but your patch will reduce the possibility.

Thanks,
Alek

> Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
> Cc: Feng Tang <feng.tang@...el.com>
> Cc: Alek Du <alek.du@...el.com>
> Cc: Alan Cox <alan@...rguk.ukuu.org.uk>
> 
> ---
>  drivers/gpio/langwell_gpio.c |   13 ++++++-------
>  1 file changed, 6 insertions(+), 7 deletions(-)
> 
> Index: linux-2.6-tip/drivers/gpio/langwell_gpio.c
> ===================================================================
> --- linux-2.6-tip.orig/drivers/gpio/langwell_gpio.c
> +++ linux-2.6-tip/drivers/gpio/langwell_gpio.c
> @@ -190,23 +190,22 @@ static void lnw_irq_handler(unsigned irq
>  	struct irq_data *data = irq_desc_get_irq_data(desc);
>  	struct lnw_gpio *lnw = irq_data_get_irq_handler_data(data);
>  	struct irq_chip *chip = irq_data_get_irq_chip(data);
> -	u32 base, gpio, gedr_v;
> +	u32 base, gpio, mask;
>  	unsigned long pending;
>  	void __iomem *gedr;
>  
>  	/* check GPIO controller to check which pin triggered the interrupt */
>  	for (base = 0; base < lnw->chip.ngpio; base += 32) {
>  		gedr = gpio_reg(&lnw->chip, base, GEDR);
> -		gedr_v = pending = readl(gedr);
> -		if (!gedr_v)
> -			continue;
> +		pending = readl(gedr);
>  		while (pending) {
>  			gpio = __ffs(pending) - 1;
> -			pending &= ~BIT(gpio);
> +			mask = BIT(gpio);
> +			pending &= ~mask;
> +			/* Clear before handling so we can't lose an edge */
> +			writel(mask, gedr);
>  			generic_handle_irq(lnw->irq_base + base + gpio);
>  		}
> -		/* clear the edge detect status bit */
> -		writel(gedr_v, gedr);
>  	}
>  
>  	chip->irq_eoi(data);
> 
> 

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