lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <4D9BA9FA.4010405@zytor.com>
Date:	Tue, 05 Apr 2011 16:47:06 -0700
From:	"H. Peter Anvin" <hpa@...or.com>
To:	"Rafael J. Wysocki" <rjw@...k.pl>
CC:	Ingo Molnar <mingo@...e.hu>,
	Stefano Stabellini <stefano.stabellini@...citrix.com>,
	"x86@...nel.org" <x86@...nel.org>,
	"yinghai@...nel.org" <yinghai@...nel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Greg KH <gregkh@...e.de>,
	"lkml20101129@...ton.leun.net" <lkml20101129@...ton.leun.net>,
	stable kernel team <stable@...nel.org>,
	Jeremy Fitzhardinge <Jeremy.Fitzhardinge@...rix.com>
Subject: Re: [PATCH urgent] x86: Save cr4 to mmu_cr4_features at boot time

On 04/04/2011 11:43 PM, Rafael J. Wysocki wrote:
> On Tuesday, April 05, 2011, H. Peter Anvin wrote:
>> On 04/04/2011 11:29 PM, Rafael J. Wysocki wrote:
>>>>
>>>> Peter very consciously did not mark the fix for this commit as -stable 
>>>> material. It was ineligible for -stable for multiple reasons: it by no means 
>>>> fixed a 2.6.39 regression and the fix was literally just a few days old.
>>>
>>> Has this issue been resolved in the mainline, BTW?
>>>
>>
>> Just to refresh my memory... is this an issue in mainline, or is it only
>> a problem in the backport (I'm wondering if the trampoline unification
>> patches might have accidentally solved the issue)?
> 
> 
> The problem is in mainline too, please fix ASAP.
> 

For the suspend/resume case this seems like the sanest way to fix it in
my opinion.  However, I am a bit concerned since I'm still not sure
we're programming registers in the correct order, that is:

MISC_ENABLE -> EFER -> cr4 -> cr3 -> cr0

I will look at this issue later this evening, but I wanted your opinion
on it.

	-hpa

View attachment "diff" of type "text/plain" (599 bytes)

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ