linux-kernel - Re: [regression 2.6.39-rc2][bisected] "perf, x86: P4 PMU - Read proper MSR register to catch" and NMIs

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Message-ID: <20110414064737.GB15535@elte.hu>
Date:	Thu, 14 Apr 2011 08:47:37 +0200
From:	Ingo Molnar <mingo@...e.hu>
To:	Cyrill Gorcunov <gorcunov@...nvz.org>,
	Peter Zijlstra <a.p.zijlstra@...llo.nl>
Cc:	maciej.rutecki@...il.com, Shaun Ruffell <sruffell@...ium.com>,
	Don Zickus <dzickus@...hat.com>, linux-kernel@...r.kernel.org,
	Lin Ming <ming.m.lin@...el.com>
Subject: Re: [regression 2.6.39-rc2][bisected] "perf, x86: P4 PMU - Read
 proper MSR register to catch" and NMIs


* Cyrill Gorcunov <gorcunov@...nvz.org> wrote:

> -	apic_write(APIC_LVTPC, APIC_DM_NMI);
> 
>  	handled = x86_pmu.handle_irq(args->regs);
>  	if (!handled)
>  		return NOTIFY_DONE;
> 
> +	/*
> +	 * Unmasking should be done after IRQ handled, otherwise
> +	 * there is a race between clearing of counter overflow
> +	 * flag and LTV entry unmasking (which might lead to double
> +	 * NMIs generation).
> +	 */
> +	apic_write(APIC_LVTPC, APIC_DM_NMI);

Here we could leak a masked IRQ through the !handled path. If we got a LVTPC 
irq we better handle it and unmask the LVTPC unconditionally - regardless of 
whether we consider it 'handled' or not from the kernel POV ...

Thanks,

	Ingo
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