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Message-ID: <4DAC5E70.6040204@zytor.com>
Date:	Mon, 18 Apr 2011 08:53:20 -0700
From:	"H. Peter Anvin" <hpa@...or.com>
To:	"Roedel, Joerg" <Joerg.Roedel@....com>
CC:	Ingo Molnar <mingo@...hat.com>,
	Thomas Gleixner <tglx@...utronix.de>,
	"x86@...nel.org" <x86@...nel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"stable@...nel.org" <stable@...nel.org>
Subject: Re: [PATCH 4/4] x86, gart: Make sure GART does not map physmem above
 1TB

On 04/18/2011 07:52 AM, Roedel, Joerg wrote:
>>
>> Where does this limit come from?
> 
> From the hardware. A GART PTE is only 32 bits in size so that it cannot
> be expanded. The physical address bits 32-39 are mapped 11:4 in the PTE.
> This can not be architecturally expanded to more than 40 physical bits.
> 

AFAIK the GART format is implementation-specific (unless some standard
crept up when I wasn't looking -- this happens from time to time); this
file seems, despite its generic name, to be AMD K8 specific.

	-hpa

-- 
H. Peter Anvin, Intel Open Source Technology Center
I work for Intel.  I don't speak on their behalf.

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