linux-kernel - Re: [Linaro-mm-sig] [RFC] ARM DMA mapping TODO, v1

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Message-ID: <20110429075958.GV17290@n2100.arm.linux.org.uk>
Date:	Fri, 29 Apr 2011 08:59:58 +0100
From:	Russell King - ARM Linux <linux@....linux.org.uk>
To:	Thomas Hellstrom <thellstrom@...are.com>
Cc:	Benjamin Herrenschmidt <benh@...nel.crashing.org>,
	Jerome Glisse <j.glisse@...il.com>,
	linaro-mm-sig@...ts.linaro.org, Arnd Bergmann <arnd@...db.de>,
	linux-kernel@...r.kernel.org,
	FUJITA Tomonori <fujita.tomonori@....ntt.co.jp>,
	linux-arm-kernel@...ts.infradead.org
Subject: Re: [Linaro-mm-sig] [RFC] ARM DMA mapping TODO, v1

On Fri, Apr 29, 2011 at 07:50:12AM +0200, Thomas Hellstrom wrote:
> However, we should be able to construct a completely generic api around  
> these operations, and for architectures that don't support them we need  
> to determine
>
> a)  Whether we want to support them anyway (IIRC the problem with PPC is  
> that the linear kernel map has huge tlb entries that are very  
> inefficient to break up?)

That same issue applies to ARM too - you'd need to stop the entire
machine, rewrite all processes page tables, flush tlbs, and only
then restart.  Otherwise there's the possibility of ending up with
conflicting types of TLB entries, and I'm not sure what the effect
of having two matching TLB entries for the same address would be.

> b)  Whether they are needed at all on the particular architecture. The  
> Intel x86 spec is, (according to AMD), supposed to forbid conflicting  
> caching attributes, but the Intel graphics guys use them for GEM. PPC  
> appears not to need it.

Some versions of the architecture manual say that having multiple
mappings with differing attributes is unpredictable.
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