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Message-ID: <20110503195254.5154.17753.stgit@beardog.cce.hp.com>
Date: Tue, 03 May 2011 14:52:54 -0500
From: "Stephen M. Cameron" <scameron@...rdog.cce.hp.com>
To: axboe@...nel.dk
Cc: mikem@...rdog.cce.hp.com, akpm@...ux-foundation.org,
thenzl@...hat.com, linux-kernel@...r.kernel.org,
smcameron@...oo.com
Subject: [PATCH 01/16] cciss: add readl after writel in interrupt mask setting
code
From: Stephen M. Cameron <scameron@...rdog.cce.hp.com>
This is to ensure the board interrupts are really off when
these functions return.
Signed-off-by: Stephen M. Cameron <scameron@...rdog.cce.hp.com>
---
drivers/block/cciss.h | 6 ++++++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/drivers/block/cciss.h b/drivers/block/cciss.h
index 554bbd9..9b49439 100644
--- a/drivers/block/cciss.h
+++ b/drivers/block/cciss.h
@@ -239,11 +239,13 @@ static void SA5_intr_mask(ctlr_info_t *h, unsigned long val)
{ /* Turn interrupts on */
h->interrupts_enabled = 1;
writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
+ (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
} else /* Turn them off */
{
h->interrupts_enabled = 0;
writel( SA5_INTR_OFF,
h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
+ (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
}
}
/*
@@ -257,11 +259,13 @@ static void SA5B_intr_mask(ctlr_info_t *h, unsigned long val)
{ /* Turn interrupts on */
h->interrupts_enabled = 1;
writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
+ (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
} else /* Turn them off */
{
h->interrupts_enabled = 0;
writel( SA5B_INTR_OFF,
h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
+ (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
}
}
@@ -271,10 +275,12 @@ static void SA5_performant_intr_mask(ctlr_info_t *h, unsigned long val)
if (val) { /* turn on interrupts */
h->interrupts_enabled = 1;
writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
+ (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
} else {
h->interrupts_enabled = 0;
writel(SA5_PERF_INTR_OFF,
h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
+ (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
}
}
--
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