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Message-ID: <BANLkTimVM2XvpJ1d9SbmAh7xZ+qSjukX+A@mail.gmail.com>
Date: Mon, 23 May 2011 11:36:02 +0200
From: Stephane Eranian <eranian@...gle.com>
To: Peter Zijlstra <peterz@...radead.org>
Cc: LKML <linux-kernel@...r.kernel.org>,
"mingo@...e.hu" <mingo@...e.hu>, Andi Kleen <andi@...stfloor.org>,
Lin Ming <ming.m.lin@...el.com>
Subject: Re: [PATCH 0/3] perf_events: update extra shared registers management (v2)
On Mon, May 23, 2011 at 11:32 AM, Peter Zijlstra <peterz@...radead.org> wrote:
> On Mon, 2011-05-23 at 11:11 +0200, Peter Zijlstra wrote:
>> + if (event->hw.extra_reg.idx == EXTRA_REG_RSP_0) {
>> + event->attr.config = 0x01bb;
>> + event->hw.extra_reg.idx = EXTRA_REG_RSP_1;
>> + event->hw.extra_reg.msr = MSR_OFFCORE_RSP_1;
>> + } else if (event->hw.extra_reg.idx == EXTRA_REG_RSP_1) {
>> + event->attr.config = 0x01b7;
>> + event->hw.extra_reg.idx = EXTRA_REG_RSP_0;
>> + event->hw.extra_reg.msr = MSR_OFFCORE_RSP_0;
>> + }
>
> clearly I meant to write:
>
> event->hw.config &= ~X86_RAW_EVENT_MASK;
> event->hw.config |= 0x01b[b7];
>
Yes, to preserve the other bits.
This patch looks good, I will test it some more.
Thanks.
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