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Message-ID: <20110525165803.GB14958@tassilo.jf.intel.com>
Date: Wed, 25 May 2011 09:58:03 -0700
From: Andi Kleen <ak@...ux.intel.com>
To: Henrique de Moraes Holschuh <hmh@....eng.br>
Cc: Ingo Molnar <mingo@...e.hu>, Andi Kleen <andi@...stfloor.org>,
x86@...nel.org, linux-kernel@...r.kernel.org,
Borislav Petkov <bp@...en8.de>
Subject: Re: [PATCH 1/3] x86, intel: Output microcode revision
> > This can happen if for example the BIOS somehow does not apply the right
> > microcode to all CPUs. It can also happen if physically different microcode
> > version CPUs are mixed. In theory people can mix steppings as well.
>
> In PRACTICE people WILL mix steppings as well.
Yes exactly. I used to have a system with one P3 supporting FXSAVE
and other not :-) I had to fix the kernel back then to support this.
The system worked perfectly fine after the kernel was fixed.
So the check proposed is a bad idea. It would trigger
on real boxes which don't have any obvious problems.
-Andi
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