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Message-ID: <1309338174.6701.929.camel@twins>
Date: Wed, 29 Jun 2011 11:02:54 +0200
From: Peter Zijlstra <a.p.zijlstra@...llo.nl>
To: Joerg Roedel <joro@...tes.org>
Cc: Joerg Roedel <joerg.roedel@....com>,
Paul Mackerras <paulus@...ba.org>, Ingo Molnar <mingo@...e.hu>,
Arnaldo Carvalho de Melo <acme@...stprotocols.net>,
linux-kernel@...r.kernel.org, kvm@...r.kernel.org,
Avi Kiviti <avi@...hat.com>
Subject: Re: [PATCH 0/5] perf support for amd guest/host-only bits v2
On Tue, 2011-06-28 at 18:10 +0200, Joerg Roedel wrote:
> On Fri, Jun 17, 2011 at 03:37:29PM +0200, Joerg Roedel wrote:
> > this is the second version of the patch-set to support the AMD
> > guest-/host only bits in the performance counter MSRs. Due to lack of
> > time I havn't looked into emulating support for this feature on Intel or
> > other architectures, but the other comments should be worked in. The
> > changes to v1 include:
> >
> > * Rebased patches to v3.0-rc3
> > * Allow exclude_guest and exclude_host set at the same time
> > * Reworked event-parse logic for the new exclude-bits
> > * Only count guest-events per default from perf-kvm
>
> Hi Peter, Ingo,
>
> have you had a chance to look at this patch-set? Are any changes
> required?
I would feel a lot more comfortable by having it implemented on all of
x86 as well as at least one !x86 platform. Avi graciously volunteered
for the Intel bits.
Paulus, I hear from benh that you're also responsible for the ppc-kvm
bits, could you possibly find some time to implement this feature for
ppc?
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