linux-kernel - Re: [PATCH 1/4] perf: Add memory load/store events generic code

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Message-Id: <1309866860.2381.1.camel@localhost>
Date:	Tue, 05 Jul 2011 19:54:20 +0800
From:	Lin Ming <ming.m.lin@...el.com>
To:	Peter Zijlstra <a.p.zijlstra@...llo.nl>
Cc:	Ingo Molnar <mingo@...e.hu>, Andi Kleen <andi@...stfloor.org>,
	Stephane Eranian <eranian@...gle.com>,
	Arnaldo Carvalho de Melo <acme@...stprotocols.net>,
	linux-kernel <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/4] perf: Add memory load/store events generic code

On Mon, 2011-07-04 at 19:16 +0800, Peter Zijlstra wrote:
> On Mon, 2011-07-04 at 08:02 +0000, Lin Ming wrote:
> > +#define MEM_STORE_DCU_HIT              (1ULL << 0)
> 
> I'm pretty sure that's not Dublin City University, but what is it?
> Data-Cache-Unit? what does that mean, L1/L2 or also L3? 
> 
> > +#define MEM_STORE_STLB_HIT             (1ULL << 1)
> 
> What's an sTLB? I know iTLB and dTLB's but sTLBs I've not heard of yet.
> 
> > +#define MEM_STORE_LOCKED_ACCESS                (1ULL << 2) 
> 
> Presumably that's about LOCK'ed ops?
> 
> So now you're just tacking bits on the end without even attempting to
> generalize/unify things, not charmed at all.

Any idea on the more useful store bits encoding?

Thanks,
Lin Ming


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