linux-kernel - Re: [PATCH 3/4] perf, x86: Add Intel SandyBridge pricise store support

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Message-ID: <1310374337.13309.28.camel@twins>
Date:	Mon, 11 Jul 2011 10:52:17 +0200
From:	Peter Zijlstra <a.p.zijlstra@...llo.nl>
To:	Lin Ming <ming.m.lin@...el.com>
Cc:	Ingo Molnar <mingo@...e.hu>, Andi Kleen <andi@...stfloor.org>,
	Stephane Eranian <eranian@...gle.com>,
	Arnaldo Carvalho de Melo <acme@...stprotocols.net>,
	linux-kernel <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 3/4] perf, x86: Add Intel SandyBridge pricise store
 support

On Mon, 2011-07-11 at 16:57 +0800, Lin Ming wrote:
> On Mon, 2011-07-11 at 16:32 +0800, Peter Zijlstra wrote:
> > On Mon, 2011-07-04 at 08:02 +0000, Lin Ming wrote:
> > > Implements Intel memory store event for SandyBridge.
> > > 
> > > $ perf mem -t store record make -j8
> > 
> > 
> > I was just looking through the Intel SDM, and stumbled upon:
> > 
> > C0H	01H	INST_RETIRED.PREC_DIST
> > 
> > Precise instruction retired event
> > with HW to reduce effect of PEBS
> > shadow in IP distribution PMC1 only; 
> > Must quiesce other PMCs.
> > ^^^^^^^^^^^^^^^^^^^^^^^^
> > 
> > WTF!? Are they real? The implementation as provided by you doesn't do
> > that (quite understandably), but please check with the hardware folks.
> 
> This is Precise Distribution of Instructions Retired (PDIR), which is
> not related to Precise Store.

Gah right, still ridiculous constraint.
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