linux-kernel - [PATCH] x86, x2apic: Preserve high 32-bits of IA32_APIC

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Message-Id: <20110712055831.2498.78521.sendpatchset@nchumbalkar.americas.cpqcorp.net>
Date:	Tue, 12 Jul 2011 05:59:07 +0000 (UTC)
From:	Naga Chumbalkar <nagananda.chumbalkar@...com>
To:	x86@...nel.org
Cc:	Naga Chumbalkar <nagananda.chumbalkar@...com>,
	suresh.b.siddha@...el.com, linux-kernel@...r.kernel.org,
	hpa@...or.com, mingo@...e.hu, tglx@...utronix.de
Subject: [PATCH] x86, x2apic: Preserve high 32-bits of IA32_APIC_BASE MSR

If there's no special reason to zero-out the "high" 32-bits of the IA32_APIC_BASE
MSR, let's preserve it.

The x2APIC Specification doesn't explicitly state any such requirement. (Sec 2.2 
in: http://www.intel.com/Assets/PDF/manual/318148.pdf).

Signed-off-by: Naga Chumbalkar <nagananda.chumbalkar@...com>
Cc: Suresh Siddha <suresh.b.siddha@...el.com>

diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index b9338b8..f7b0c7a 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -1429,7 +1429,7 @@ void enable_x2apic(void)
 	rdmsr(MSR_IA32_APICBASE, msr, msr2);
 	if (!(msr & X2APIC_ENABLE)) {
 		printk_once(KERN_INFO "Enabling x2apic\n");
-		wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
+		wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, msr2);
 	}
 }
 #endif /* CONFIG_X86_X2APIC */
--
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