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Message-Id: <20110727214800.5CA142403FF@tassilo.jf.intel.com>
Date: Wed, 27 Jul 2011 14:48:00 -0700 (PDT)
From: Andi Kleen <andi@...stfloor.org>
To: Joerg.Roedel@....com, joerg.roedel@....com, rjw@...k.pl,
maciej.rutecki@...il.com, avi@...hat.com,
akpm@...ux-foundation.org, mingo@...e.hu, gregkh@...e.de,
ak@...ux.intel.com, linux-kernel@...r.kernel.org,
stable@...nel.org, tim.bird@...sony.com
Subject: [PATCH] [2/99] x86, amd: Use _safe() msr access for GartTlbWlk disable code
2.6.35-longterm review patch. If anyone has any objections, please let me know.
------------------
From: "Roedel, Joerg" <Joerg.Roedel@....com>
commit d47cc0db8fd6011de2248df505fc34990b7451bf upstream.
The workaround for Bugzilla:
https://bugzilla.kernel.org/show_bug.cgi?id=33012
introduced a read and a write to the MC4 mask msr.
Unfortunatly this MSR is not emulated by the KVM hypervisor
so that the kernel will get a #GP and crashes when applying
this workaround when running inside KVM.
This issue was reported as:
https://bugzilla.kernel.org/show_bug.cgi?id=35132
and is fixed with this patch. The change just let the kernel
ignore any #GP it gets while accessing this MSR by using the
_safe msr access methods.
Reported-by: Török Edwin <edwintorok@...il.com>
Signed-off-by: Joerg Roedel <joerg.roedel@....com>
Cc: Rafael J. Wysocki <rjw@...k.pl>
Cc: Maciej Rutecki <maciej.rutecki@...il.com>
Cc: Avi Kivity <avi@...hat.com>
Cc: Andrew Morton <akpm@...ux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@...e.hu>
Signed-off-by: Greg Kroah-Hartman <gregkh@...e.de>
Signed-off-by: Andi Kleen <ak@...ux.intel.com>
---
arch/x86/kernel/cpu/amd.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
Index: linux-2.6.35.y/arch/x86/kernel/cpu/amd.c
===================================================================
--- linux-2.6.35.y.orig/arch/x86/kernel/cpu/amd.c
+++ linux-2.6.35.y/arch/x86/kernel/cpu/amd.c
@@ -585,10 +585,13 @@ static void __cpuinit init_amd(struct cp
* Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
*/
u64 mask;
+ int err;
- rdmsrl(MSR_AMD64_MCx_MASK(4), mask);
- mask |= (1 << 10);
- wrmsrl(MSR_AMD64_MCx_MASK(4), mask);
+ err = rdmsrl_safe(MSR_AMD64_MCx_MASK(4), &mask);
+ if (err == 0) {
+ mask |= (1 << 10);
+ checking_wrmsrl(MSR_AMD64_MCx_MASK(4), mask);
+ }
}
}
--
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