linux-kernel - Re: [GIT PULL] Lockless SLUB slowpaths for v3.1-rc1

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Message-ID: <m2livez6vl.fsf@firstfloor.org>
Date:	Sun, 31 Jul 2011 10:39:58 -0700
From:	Andi Kleen <andi@...stfloor.org>
To:	Linus Torvalds <torvalds@...ux-foundation.org>
Cc:	Pekka Enberg <penberg@...nel.org>, cl@...ux-foundation.org,
	akpm@...ux-foundation.org, rientjes@...gle.com, hughd@...gle.com,
	linux-kernel@...r.kernel.org, linux-mm@...ck.org,
	kamezawa.hiroyu@...fujitsu.com, kosaki.motohiro@...fujitsu.com,
	yinghan@...gle.com
Subject: Re: [GIT PULL] Lockless SLUB slowpaths for v3.1-rc1

Linus Torvalds <torvalds@...ux-foundation.org> writes:

> On Sat, Jul 30, 2011 at 8:27 AM, Linus Torvalds
> <torvalds@...ux-foundation.org> wrote:
>>
>> Do we allocate the page map array sufficiently aligned that we
>> actually don't ever have the case of straddling a cacheline? I didn't
>> check.
>
> Oh, and another thing worth checking: did somebody actually check the
> timings for:

I would like to see a followon patch that moves the mem_cgroup
pointer back into struct page. Copying some mem_cgroup people.

>
>  - *just* the alignment change?
>
>    IOW, maybe some of the netperf improvement isn't from the lockless
> path, but exactly from 'struct page' always being in a single
> cacheline?
>
>  - check performance with cmpxchg16b *without* the alignment.
>
>    Sometimes especially intel is so good at unaligned accesses that
> you wouldn't see an issue. Now, locked ops are usually special (and

As Eric pointed out CMPXCHG16B requires alignment, it #GPs otherwise.

-Andi
-- 
ak@...ux.intel.com -- Speaking for myself only
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