linux-kernel - Re: [perf] enable raw OFFCORE_EVENTS for non-perf userspace

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Message-ID: <1312473330.16729.42.camel@twins>
Date:	Thu, 04 Aug 2011 17:55:30 +0200
From:	Peter Zijlstra <a.p.zijlstra@...llo.nl>
To:	Vince Weaver <vweaver1@...s.utk.edu>
Cc:	linux-kernel@...r.kernel.org, Paul Mackerras <paulus@...ba.org>,
	Ingo Molnar <mingo@...e.hu>,
	Arnaldo Carvalho de Melo <acme@...stprotocols.net>
Subject: Re: [perf] enable raw OFFCORE_EVENTS for non-perf userspace

On Wed, 2011-08-03 at 12:05 -0400, Vince Weaver wrote:
> Hello
> 
> I propose we just enable raw OFFCORE_EVENT support and get it over with.
> 
> There is a lot of demand for this from PAPI users, and so we encourage 
> them to apply the below patch.  PAPI supports this out of the box.
> 
> The current "block" against using this feature *DOES NOT WORK*.
> It silently fails if you try to use the config1 field to set it.
> 
> Even worse, if some previous user has set the OFFCORE_RSP_0 msr
> (say by running "perf stat -e LLC-load-misses") then
> the msr *stays set* and if you try to set the config1 field on your own
> it looks like it worked, but instead it is using whatever value the
> kernel last used.
> 
> So there's a lot of userspace confusion about this, and you can't even 
> reliably tell if the feature is turned off or not because it fails 
> silently in unpredictable ways.


> diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
> index 4ee3abf..28f9ca9 100644
> --- a/arch/x86/kernel/cpu/perf_event.c
> +++ b/arch/x86/kernel/cpu/perf_event.c
> @@ -604,12 +604,8 @@ static int x86_setup_perfctr(struct perf_event *event)
>  			return -EOPNOTSUPP;
>  	}
>  
> -	/*
> -	 * Do not allow config1 (extended registers) to propagate,
> -	 * there's no sane user-space generalization yet:
> -	 */
>  	if (attr->type == PERF_TYPE_RAW)
> -		return 0;
> +		return x86_pmu_extra_regs(event->attr.config, event);
>  
>  	if (attr->type == PERF_TYPE_HW_CACHE)
>  		return set_ext_hw_attr(hwc, event);


I'm inclined to merge this, aside from snb, the offcore stuff is
actually quite usable now. Ingo can we somehow persuade you?

Anybody who knows how to program the snb offcore please tell. I mean we
have all the code to poke at the right registers, and the SDM lists all
the various bits that go where and a few constraints on how to combine
said bits, but I've really no idea what any of it means.


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