linux-kernel - Re: [perf] enable raw OFFCORE_EVENTS for non-perf userspace

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Message-ID: <20110805094942.GB2420@elte.hu>
Date:	Fri, 5 Aug 2011 11:49:42 +0200
From:	Ingo Molnar <mingo@...e.hu>
To:	Peter Zijlstra <a.p.zijlstra@...llo.nl>
Cc:	Vince Weaver <vweaver1@...s.utk.edu>, linux-kernel@...r.kernel.org,
	Paul Mackerras <paulus@...ba.org>,
	Arnaldo Carvalho de Melo <acme@...stprotocols.net>,
	Arnaldo Carvalho de Melo <acme@...hat.com>,
	Frédéric Weisbecker <fweisbec@...il.com>
Subject: Re: [perf] enable raw OFFCORE_EVENTS for non-perf userspace


* Peter Zijlstra <a.p.zijlstra@...llo.nl> wrote:

> On Wed, 2011-08-03 at 12:05 -0400, Vince Weaver wrote:
> > Hello
> > 
> > I propose we just enable raw OFFCORE_EVENT support and get it over with.
> > 
> > There is a lot of demand for this from PAPI users, and so we encourage 
> > them to apply the below patch.  PAPI supports this out of the box.
> > 
> > The current "block" against using this feature *DOES NOT WORK*.
> > It silently fails if you try to use the config1 field to set it.
> > 
> > Even worse, if some previous user has set the OFFCORE_RSP_0 msr
> > (say by running "perf stat -e LLC-load-misses") then
> > the msr *stays set* and if you try to set the config1 field on your own
> > it looks like it worked, but instead it is using whatever value the
> > kernel last used.
> > 
> > So there's a lot of userspace confusion about this, and you can't even 
> > reliably tell if the feature is turned off or not because it fails 
> > silently in unpredictable ways.
> 
> 
> > diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
> > index 4ee3abf..28f9ca9 100644
> > --- a/arch/x86/kernel/cpu/perf_event.c
> > +++ b/arch/x86/kernel/cpu/perf_event.c
> > @@ -604,12 +604,8 @@ static int x86_setup_perfctr(struct perf_event *event)
> >  			return -EOPNOTSUPP;
> >  	}
> >  
> > -	/*
> > -	 * Do not allow config1 (extended registers) to propagate,
> > -	 * there's no sane user-space generalization yet:
> > -	 */
> >  	if (attr->type == PERF_TYPE_RAW)
> > -		return 0;
> > +		return x86_pmu_extra_regs(event->attr.config, event);
> >  
> >  	if (attr->type == PERF_TYPE_HW_CACHE)
> >  		return set_ext_hw_attr(hwc, event);
> 
> 
> I'm inclined to merge this, aside from snb, the offcore stuff is 
> actually quite usable now. Ingo can we somehow persuade you?

Sure, i think we are almost there, the only missing bit i see is to 
add the now generalized NUMA node bits to tools/perf/ so that it can 
be tested easily and then we can enable the raw bits as well.

It was supposed to be added alongside of:

  89d6c0b: perf, arch: Add generic NODE cache events

what happened to that? If someone wants to accelerate the raw events 
enabling then that should be an easy thing to fix.

Thanks,

	Ingo
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