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Message-ID: <alpine.DEB.2.00.1108101328440.22769@cl320.eecs.utk.edu>
Date: Wed, 10 Aug 2011 13:40:31 -0400
From: Vince Weaver <vweaver1@...s.utk.edu>
To: <linux-kernel@...r.kernel.org>
CC: <will.deacon@....com>, sam wang <linux.swang@...il.com>,
Ingo Molnar <mingo@...e.hu>,
Peter Zijlstra <a.p.zijlstra@...llo.nl>,
Paul Mackerras <paulus@...ba.org>,
Arnaldo Carvalho de Melo <acme@...stprotocols.net>,
Stephane Eranian <eranian@...il.com>
Subject: [patch] perf: ARMv7 wrong "branches" generalized instruction
Hello
Sam Wang reported to me that my perf_event validation tests were failing
with branches on ARM Cortex A9.
It turns out the branches event used (ARMV7_PERFCTR_PC_WRITE) only seems
to count taken branches.
ARMV7_PERFCTR_PC_IMM_BRANCH seems to do a better job of counting both
taken and not-taken. So I've attached a patch to change the definition
for Cotex A9.
This might be needed for Cortex A8 but I don't have a machine to test on
(yet).
I'm assuming this is a proper fix. The "generalized" events aren't
defined very well so there's always some wiggle room about what they mean.
Patch tested on a Pandaboard.
The test code looks like this. There should be 500,000*3 branches. But
the second branch (the not taken "bge test_jmp2") is not counted with
PC_WRITE.
asm( "\teor r3,r3,r3\n"
"\tldr r3,=500000\n"
"test_loop:\n"
"\tB test_jmp\n"
"\tnop\n"
"test_jmp:\n"
"\teor r2,r2,r2\n"
"\tcmp r2,#1\n"
"\tbge test_jmp2\n"
"\tnop\n"
"\tadd r2,r2,#1\n"
"test_jmp2:\n"
"\tsub r3,r3,#1\n"
"\tcmp r3,#1\n"
"\tbgt test_loop\n"
: /* no output registers */
: /* no inputs */
: "cc", "r2", "r3" /* clobbered */
);
Vince
vweaver1@...s.utk.edu
Signed-off-by: Vince Weaver <vweaver1@...s.utk.edu>
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index 4c85183..4d11bd5 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -323,7 +323,7 @@ static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = {
ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE,
[PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_COHERENT_LINE_HIT,
[PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_COHERENT_LINE_MISS,
- [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
+ [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_IMM_BRANCH,
[PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
[PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES,
};
--
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