linux-kernel - Re: [PATCH v2 2/2] crypto, x86: SSSE3 based SHA1 implementation for x86-64

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Message-ID: <20110811150840.GA14503@gondor.apana.org.au>
Date:	Thu, 11 Aug 2011 23:08:40 +0800
From:	Herbert Xu <herbert@...dor.apana.org.au>
To:	Andy Lutomirski <luto@....EDU>
Cc:	Mathias Krause <minipli@...glemail.com>,
	"David S. Miller" <davem@...emloft.net>,
	linux-crypto@...r.kernel.org,
	Maxim Locktyukhin <maxim.locktyukhin@...el.com>,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 2/2] crypto, x86: SSSE3 based SHA1 implementation
	for x86-64

On Thu, Aug 11, 2011 at 10:50:49AM -0400, Andy Lutomirski wrote:
>
>> This is pretty similar to the situation with the Intel AES code.
>> Over there they solved it by using the asynchronous interface and
>> deferring the processing to a work queue.
>
> I have vague plans to clean up extended state handling and make  
> kernel_fpu_begin work efficiently from any context.  (i.e. the first  
> kernel_fpu_begin after a context switch could take up to ~60 ns on Sandy  
> Bridge, but further calls to kernel_fpu_begin would be a single branch.)

This is all well and good but you still need to deal with the
case of !irq_fpu_usable.

Cheers,
-- 
Email: Herbert Xu <herbert@...dor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
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