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Message-ID: <alpine.DEB.2.00.1108251341230.27407@router.home>
Date: Thu, 25 Aug 2011 13:46:27 -0500 (CDT)
From: Christoph Lameter <cl@...ux.com>
To: James Bottomley <James.bottomley@...senPartnership.com>
cc: Peter Zijlstra <peterz@...radead.org>,
Andrew Morton <akpm@...ux-foundation.org>,
Greg Thelen <gthelen@...gle.com>, linux-kernel@...r.kernel.org,
linux-mm@...ck.org,
KAMEZAWA Hiroyuki <kamezawa.hiroyu@...fujitsu.com>,
Balbir Singh <bsingharora@...il.com>,
Daisuke Nishimura <nishimura@....nes.nec.co.jp>,
linux-arch@...r.kernel.org
Subject: Re: [PATCH] memcg: remove unneeded preempt_disable
On Thu, 25 Aug 2011, James Bottomley wrote:
> >Well then what is "really risc"? RISC is an old beaten down marketing
> >term
> >AFAICT and ARM claims it too.
>
> Reduced Instruction Set Computer. This is why we're unlikely to have
> complex atomic instructions: the principle of risc is that you build
> them up from basic ones.
RISC cpus have instruction to construct complex atomic actions by the cpu
as I have shown before for ARM.
Principles always have exceptions to them.
(That statement in itself is a principle that should have an exception I
guess. But then language often only makes sense when it contains
contradictions.)
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