linux-kernel - Re: [PATCH 1/3] add dma_coherent_write

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Message-ID: <CAHkRjk7QWCkKKT8BErRsS_ZASChOyGuh04PM2qP3pQnp+KhJVw@mail.gmail.com>
Date:	Tue, 6 Sep 2011 15:30:42 +0100
From:	Catalin Marinas <catalin.marinas@....com>
To:	Mark Salter <msalter@...hat.com>
Cc:	Michał Mirosław <mirqus@...il.com>,
	ming.lei@...onical.com, stern@...land.harvard.edu,
	linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH 1/3] add dma_coherent_write_sync to DMA API

(coming late to this thread due to holidays)

2011/9/1 Mark Salter <msalter@...hat.com>:
> On Thu, 2011-09-01 at 11:57 +0200, Michał Mirosław wrote:
>> BTW, if there's no time limit on write buffers flushing, or if write
>> buffers can cause reordering of the writes, then the memory accesses
>> need to be managed just like non-DMA-coherent memory. So what differs
>> then in DMA-coherent vs non-DMA-coherent mappings then?
>
> My understanding is that ordering is preserved, but an ARM guy should
> probably verify that.

On ARMv6 onwards the coherent DMA is Normal Non-cacheable memory and
this is buffered and can be reordered.

-- 
Catalin
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