lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20110915135310.GA25690@S2100-06.ap.freescale.net>
Date:	Thu, 15 Sep 2011 21:53:12 +0800
From:	Shawn Guo <shawn.guo@...escale.com>
To:	Rob Herring <robherring2@...il.com>
CC:	<linux-arm-kernel@...ts.infradead.org>,
	<devicetree-discuss@...ts.ozlabs.org>,
	<linux-kernel@...r.kernel.org>,
	Rob Herring <rob.herring@...xeda.com>
Subject: Re: [PATCH 0/5] GIC OF bindings

On Wed, Sep 14, 2011 at 11:31:35AM -0500, Rob Herring wrote:
> From: Rob Herring <rob.herring@...xeda.com>
> 
> This series introduces of_irq_init to scan the device tree for interrupt
> controller nodes and call their init functions in proper order. The GIC
> init function is then called from this function. The platform code then
> looks something like this:
> 
> const static struct of_device_id irq_match[] = {
> 	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
> 	{}
> };
> 
> static void __init highbank_init_irq(void)
> {
> 	of_irq_init(irq_match);
> }
> 
> The binding for GIC PPIs is now done with a 3rd interrupt cell to specify
> a cpu mask for which cpu the PPI is connected to. This was discussed at LPC
> and suggested by Grant.
> 
> I dropped the public intc_desc struct. The the interrupt controller's node
> and the interrupt parent's node are passed in directly to the controller's
> init function. The linux irq assignment is now done dynamically using
> irq_alloc_descs.
> 
> The first 2 patches are minor fixes to irqdomains.
> 
> Rob
> 
> Rob Herring (5):
>   irq: add declaration of irq_domain_simple_ops to irqdomain.h
>   irq: fix existing domain check in irq_domain_add
>   of/irq: introduce of_irq_init
>   ARM: gic: allow irq_start to be 0
>   ARM: gic: add OF based initialization
> 
>  Documentation/devicetree/bindings/arm/gic.txt |   53 ++++++++++++++
>  arch/arm/common/gic.c                         |   57 +++++++++++++--
>  arch/arm/include/asm/hardware/gic.h           |   10 +++
>  drivers/of/irq.c                              |   96 +++++++++++++++++++++++++
>  include/linux/irqdomain.h                     |    1 +
>  include/linux/of_irq.h                        |    1 +
>  kernel/irq/irqdomain.c                        |    2 +-
>  7 files changed, 214 insertions(+), 6 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/gic.txt

On imx6q:

Tested-by: Shawn Guo <shawn.guo@...aro.org>

-- 
Regards,
Shawn

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ