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Message-ID: <20110918062144.GF3523@ponder.secretlab.ca>
Date:	Sun, 18 Sep 2011 00:21:44 -0600
From:	Grant Likely <grant.likely@...retlab.ca>
To:	Dave Martin <dave.martin@...aro.org>
Cc:	"Cousson, Benoit" <b-cousson@...com>,
	Rob Herring <robherring2@...il.com>,
	"marc.zyngier@....com" <marc.zyngier@....com>,
	"devicetree-discuss@...ts.ozlabs.org" 
	<devicetree-discuss@...ts.ozlabs.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Rob Herring <rob.herring@...xeda.com>,
	Thomas Abraham <thomas.abraham@...aro.org>,
	"jamie@...ieiles.com" <jamie@...ieiles.com>,
	"shawn.guo@...aro.org" <shawn.guo@...aro.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH 5/5] ARM: gic: add OF based initialization

On Fri, Sep 16, 2011 at 05:09:39PM +0100, Dave Martin wrote:
> For now, we express the mapping by putting an interrupt-map in the
> core-tile DT, but this feels inelegant as well as wasteful -- expressing
> "+ 32" using a table which is about 1K in size and duplicates that
> information 43 times.
> 
> Using a dedicated irq domain or a fake interrupt controller node to
> encapsulate the motherboard interrupts feels like a cleaner approach,
> but for now I'm not clear on the best way to do it.

An irq nexus node would indeed be something to investigate for your
particular case.  Look for examples of interrupt-map.  It is most
often used for handling IRQ swizzling on PCI busses.

g.

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