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Date:	Thu, 22 Sep 2011 20:03:30 -0700
From:	Praveen G K <praveen.gk@...il.com>
To:	Qiang LIU <godliuqiang@...il.com>
Cc:	linux-kernel@...r.kernel.org
Subject: Re: eMMC low write speed

Hi Qiang,





On Thu, Sep 22, 2011 at 7:16 PM, Qiang LIU <godliuqiang@...il.com> wrote:
> Hi,
>
> I suggest you change another eMMC card or try SDHC card. It seems like
> a card issue.

Thanks for the response.  So, do you think this has nothing to do with
the caching or any such issues, since it is only every 63rd and 64th
transfer causing this issue?

> What's your environment. Which mode is the host controller, DMA or PIO?

The host controller is in the DMA mode.

> About the bounce buffer, I think is a trade off, if you enlarge its size.
> Sometimes
> will rise timeout error (2s, other polling thread won't gain the host
> controller).
>
> 2011/9/23 Praveen G K <praveen.gk@...il.com>
>>
>> Hello all,
>>
>> I am working on the block driver module of the eMMC driver.  I am
>> seeing very low write speed for eMMC transfers.  On further debugging,
>> I observed that every 63rd and 64th transfer takes a long time.  I
>> have tabulated this by noting the time interval between when CMD 25
>> (multi block write command) is sent and when DATA_END interrupt is
>> received.  In normal cases, to transfer 64k (128 blocks of data), it
>> takes about 2.5ms.  But, under the really slow transfer speed cases,
>> it takes about 250-350ms to get the data_end interrupt after the multi
>> block write command is sent.  In some cases, it takes a longer time.
>> This radically reduces the throughput of the transfers.
>>
>> I have also enabled the bounce buffers.  As a side question, can
>> somebody please tell me why the bounce buffer is restricted to 64kB?
>>
>> Thanks in advance for any help that you can provide me on this issue.
>> Also, please include my email id in the cc field when replying to this
>> email since I am not subscribed to this mailing list.
>>
>> Thanks,
>> Praveen Krishnan
>> --
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>
>
>
> --
> Best Regards
> Onizuka Eiji
>
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